Circuits designed with MOS transistors often have need for high-voltage handling devices. The high-voltage devices are used in various components of the circuit, such as band-gap reference circuits, voltage clamps, and ESD protection circuits. In order to keep fabrication costs low and maintain compact circuit design, high-voltage handling devices are typically fabricated with the same processing steps as those employed to fabricate the functional components of the MOS circuit. This means that rather than employing specific fabrication steps to form devices dedicated to the particular demands of the high-voltage handling device, the inherent parasitic devices within an MOS transistor are exploited to perform the high-voltage handling function. This is, in part, a result of the difficulty of fabricating traditional bipolar transistors in modern MOS circuit technology. For example, the retrograde well structure used in advanced MOS circuits limits the current gain of vertical bipolar transistors that share the retrograde well with the MOS transistors. Further, lateral bipolar transistors cannot be used where associated MOS gate capacitors would be damaged by the high-voltages supported by the lateral bipolar transistors.
In many MOS circuits, multiple high-voltage handling devices are necessary to protect the MOS circuit against damage from an ESD event. Devices for protecting MOS circuits against ESD events include resistors, serially or parallel connected diodes, silicon controlled rectifiers, and MOS transistors acting as lateral bipolar devices. A representative conventional MOS device for use in an ESD protection circuit is illustrated in FIG. 1. The MOS device includes a source region 10 and a drain region 12 formed within a semiconductor substrate 14. A gate electrode 16 overlies the surface of semiconductor substrate 14 and is separated therefrom by a gate oxide layer 18. Sidewall spacers 20 reside adjacent to the vertical edges of gate electrode 16 and also overlie gate oxide layer 18. Sidewall spacers 20 are separated from gate electrode 16 by an oxide layer 22. A channel region 24 resides in substrate 14 between source region 10 and drain region 12. Channel region 24 also includes lightly-doped drain (LDD) regions 26 and pocket regions 28.
The MOS transistor illustrated in FIG. 1 is typical of a state-of-the-art MOS transistor found in high performance MOS circuits. Such transistors typically have gate lengths on the order of a few tenths of microns and are intended for high-speed operation. MOS devices, such as the MOS illustrated in FIG. 1, are designed to avoid voltage breakdown under normal operating conditions. During an ESD event, however, the MOS transistor illustrated in FIG. 1 will conduct significant current by means of a parasitic lateral bipolar mechanism.
The parasitic action of MOS transistor 30 is illustrated in the equivalent circuit diagram of FIG. 2. The bipolar current conduction is shown from drain region 10 (drain/collector) to source region 12 (source/emitter). Gate electrode 16 is capacitively coupled to substrate 14 (substrate/base) and to drain region 10 and source region 12 by capacitances C1, C2, and C3. The capacitances C1, C2, and C3 are a parasitic and arise through the p-n junctions created in the substrate by source and drain regions 10 and 12, LDD regions 26, and pocket regions 28. These parasitic capacitances degrade the circuit speed and reduce the breakdown voltage of the transistor.
The transistor illustrated in FIG. 1 is a poor bipolar transistor in part because it is designed for optimum performance as a high-speed MOS transistor. Accordingly, this MOS transistor has LDD and pocket regions in the channel and a very short channel length. The MOS transistor also has good gate-drain overlap, and a very thin gate oxide layer. These features combine to produce an MOS transistor having high-transconductance. At the same time, the very features that provide improved MOS transistor performance reduce the MOS transistor's ability to function as a parasitic bipolar transistor. In an attempt to overcome some of the performance problems associated with the transistor shown in FIG. 1, transistors have been designed that remove the LDD region on the drain side of the channel. Although eliminating the LDD region on one side of the channel reduces some of the parasitic capacitance, the MOS transistor still does not exhibit optimal performance as a bipolar high-voltage handling device. Accordingly, the need existed for a lateral high-voltage junction device that can be fabricated without resort to specialized fabrication steps and that can optimally function as a lateral bipolar transistor for handling high voltage transients.